The end of frequency scaling has driven computer architects and developers to parallelism in search of performance improvements. Since multi-core processors can be inefficient and power-hungry, many have turned to specialized accelerators including GPUs and other architectures such as programmable architecture. For example, the importance of power dissipation makes the compilation of applications directly into reconfigurable hardware (Field-Programmable Gate Arrays (FPGAs)) a potential commercial target. Compilation of applications on a wide scale requires leveraging the skills of current software developers. But there is a large gap between the abstractions presented by high level programming languages and those used in hardware design.
Reconfigurable hardware can deliver impressive performance for some applications, when a highly static hardware design closely matches application logic. Obligated to express efficient static hardware structures, hardware designers cannot currently employ abstractions using dynamic features of modern programming languages.